Modern SystemVerilog simulation toolchain with a multi-stage IR pipeline and multiple backends.
// readme
Lyra: A Modern SystemVerilog Simulation Toolchain
Lyra is a SystemVerilog compiler and simulator built the way a modern language toolchain is built: around independently compilable units with explicit dependencies, where incremental and parallel compilation are constraints on the design rather than optimizations added to it later.
The goal is a fast edit-run loop rather than peak simulation speed. Those two pull in different directions, and Lyra picks the loop. A module, package, or interface compiles on its own into class-level artifacts, and instantiation, parameter binding, and hierarchy all happen when the simulation starts. Compile time then follows how many distinct units a design has, not how many instances it elaborates into.
Those commitments, and the constraints that follow from them, are stated in docs/architecture/north_star.md. Every other design document in this repository answers to that one.
Coverage is measured rather than described. Every construct Lyra handles is claimed by a case under
tests/conformance/ stating what IEEE 1800 requires of a program and checking itself…