Newborn 
RS A VHDL and Verilog compiler written from scratch in Rust, with no third-party crates: simulation, synthesis, formal verification, FPGA place-and-route, bitstream generation and JTAG programming.
HEALTH ? 87 / Healthy
Newborn RS // readme
reticle
A VHDL / Verilog compiler written from scratch in Rust, with no foreign code and no third-party crates.
Reticle is intended to grow into one self-contained hardware toolchain:
- Frontends for Verilog-2005 / synthesisable SystemVerilog and VHDL-2008, both lowering to a single intermediate representation so mixed-language designs need no special handling.
- Simulation with an event-driven 4-state simulator, VCD / FST waveforms,
and a Rust co-simulation API for writing testbenches as
#[test]s. - Synthesis with flip-flop, memory and FSM inference, an AIG-based logic optimiser, and LUT and standard-cell mapping.
- Targets for FPGA (device databases, placement constraints, an own placer and router for open families, interop with nextpnr and vendor tools) and ASIC (Liberty, LEF / DEF, static timing analysis).
- Verification through bounded model checking and equivalence checking on an in-crate SAT solver.
- IP integration: a manifest format for third-party IP, bus interface abstractions (AXI, Wishbone, APB), black-box handling for encrypted vendor cores, a static registry index, an IP-XACT importer, and a first-party IP…