// readme

VeriSim

Verilog in your browser — fully client-side. A browser-based Verilog simulator built by compiling Icarus Verilog to WebAssembly. No server, no install: edit, compile, simulate, view waveforms, and synthesize to a gate-level or RTL schematic — entirely in the page.

Live: https://senolgulgonul.github.io/verisim/


Ported toolchain

VeriSim runs Icarus Verilog version 14.0 (devel), built from upstream commit c7530db (master as of 2026-05-31, the development line after the 13.0 release), compiled to WebAssembly with Emscripten.

Icarus Verilog is three cooperating programs; each is shipped here as a separate WebAssembly module:

ProgramRoleModule
ivlpppreprocessor (macros, includes, `line directives)ivlpp.wasm / ivlpp.js
ivlcompiler — elaborates Verilog and emits a .vvp programivl.wasm / ivl.js
vvpruntime — executes the .vvp program, writes the VCDvvp.wasm / vvp.js

How it works

A normal Icarus install runs these as separate OS…